Jobs ASIC Design Engineer Physical Design Job Vacancies VHDL Verilog embedded design Verification employment placements Careers
Singapore Jobs for Engineers Design RFIC Engineer embedded design embedded development, Senior Digital Engineer, Mixed signal, chip design, chip architecture, Physical design, physical design methodology, Place & route, Front End Design,Board Development, FPGA, ASIC, VHDL, Verilog, board design, Digital Design Analog
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BSP RTOS Device Drivers Porting Embedded Java
Technical Lead - Linux & RTOS BSP & Device Drivers
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Linux BSP System Tech Lead |
System Software Engineer: BSP Security |
Linux device driver developer |
Embedded, Java Professionals |
Software Engineer C - C++ - ARM Assembly |
Senior Engineers BSP |
ASIC Design Physical Design Verification Verilog Physical Design-Backend |
Physical Design Engineer 3 - 4 Years |
Physical Design Engineer 2 - 7 years |
Lead ASIC Physical design Engineer |
Lead ASIC Physical design verification engineer |
Physical Design - Design Manager |
Verilog coder for Altera & Xilinx FPGA work |
System Verilog / Specman Vera Verification |
Design Verification System Verilog |
SoC Verification Vera/ System Verilog |
ASIC Engineer (VHDL, Verilog HDL,) |
Backend Design
HI SPEED CLOCK PHYSICAL DESIGN ENGINEER | Physical Design Engineer with First Encounter | Physical design engineer analyst | Physical design engineer | QA Engineer Backend Automation |
ASIC Design Manager - Pune ASIC Design Engineer Senior RFIC Design Engineer Senior Digital Engineer Senior Engineer Manager – R&DSenior Program Manager Chip Architects Project Managers - RTL Design Project Manager ASIC Engineers : Front End Design
Engineer Engineer Board Development Group Principal Digital Design Engineer (Mixed Signal team) RFIC Design Engineer Digital Design EngineerDigital Design Engineer (Mixed Signal team) Analogue Design Engineer
Our clients a pioneer in LAN security, provides network security systems that eliminate the risks of enabling untrusted users to conduct business on the corporate LAN.They are in search of talented engineers for the following job positions. All the job positions are for Pune.
Data Plane/Software Manager
Security Product Manager | Manager System Test and Diagnostics Verification Manager Senior Technical Support Engineer TAC | Embedded Diagnostics SW Engineer
| Software Engineer (Testing)| Software
Engineer (ECS)| Senior ASIC Verification Engineer| Signature Audit Group Sr.
Software Engineer / Software Engineer (Security) | Techncial Lead –Software Development| Software Engineer-GUI|Testing Protocols
Physical Design-Backend
Physical Design-Backend
Job Description: Physical Design-backend Strong Knowledge in timing / timing closure activities along with full design implementation experience. Exposure in low-power implementation Very good communication
Experience: 7-10 yrs
Physical Design Engineer 3 - 4 Years
Physical Design Engineer 3 - 4 Years
Job Description:
Creates bottoms-up elements of chip design including but not limited to: FET, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction, and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification.
Troubleshoots design issues and applies proactive intervention.
May schedule staffing, execution, and verification of complex chips development and execution of project methodologies and/or flow developments.
Additional qualifications include: - Proficiency in multiple levels of layout design which includes data path, register files, and standard cell designs
Proficiency in floor planning activities which include FUB-unit level assembly, routing, and integration of custom blocks in to the FC floorplan
Ability to comprehend issues of RC delay, electro-migration, self-heating, and cross capacitance
Ability to recognize failure prone layout structures, and proactively contact engineers for guidance and produce electrically robust layout Engineering Design, R & D
Experience: 3 - 4 Years
Physical Design Engineer 2 - 7 years
Physical Design Engineer 2 - 7 years
Job Description:
Experience in Synopsys ICC/ BlastFusion / Talus / SoC Encounter / Astro or equivalent, and Blast plan pro / FE Electrical. reliability analysis for variant SoCs,
Should have worked on following areas Synthesis, Floorplanning/IO/Package Planning, Place and Route, Timing / Noise / Design Closure.
Lead ASIC Physical design Engineer
Lead ASIC Physical design Engineer
Job Description Lead - PHYSICAL DESIGN Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in Place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks.
In addition to this, He/She will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors .
Requirements: Minimum 3 - 8 years of ASIC physical design experience.
Expertise in ASIC Physical Design: Floor planning, Clock Tree Synthesis, P & R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Hands on experience in Blast Fusion, Talus- magma tools will be plus Participated in a minimum of 2- 4 fullchip tapeouts will be a plus.
Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
Familiar with Physical Verification (calibre) will be a plus.
Lead ASIC Physical design verification engineer
Lead ASIC Physical design verification engineer
Lead - Physical Design Verification Will be responsible for execution of Physical verification at Full chip and block level.
Will also be responsible for physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in Place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks.
Requirements: 5 years of ASIC physical verification and design experience.
Should have hands-on experience with Mentor/ Cadence tools for Physical verification and familiarity with Cadence physical design tools.
An exposure to DFM checks and analysis will be an added advantage.
This job will require interfacing with the design teams and our fab technology team to do sign off physical verification checks for multiple foundries.
A good understanding of layout DRC rules and concepts, device identification concepts. Should have participated in 3-4 full chip tapeouts.
Experience supporting layout teams and displaying solid programming knowledge in Perl, SKILL, TCL, and/or Shell Scripting, and the physical verification languages like SVRF, SKILL. Cadence DFII framework and understand basic concepts related to gate and device-level extraction.
Familiarity with various simulation / synthesis / formal verification tools.
Must have seen multiple ASIC tape-outs with at least 1 from RTL/Netlist to full production.
Physical Design - Design Manager
Physical Design - Design Manager
Job Description: Physical Design - Design Manager -
Top Semiconductor MNC
10-to-18 years of experience
4-5 Yrs of Design Management & Technical leadership
4 -6 tapeouts with full ownership of the design
Good handling on hierarchical design with the latest technology nodes like 65nm & 40nm
Expertise in Physical design & hands-on with Timing/DFT
Keywords: Design Manager, Physical Design, Virtuoso, Encounter, P & R, PnR, APR, Calibre, Floorplan, IR Drop, Physical Verification, RTL, GDS, Netlist, Timing, STA, Primetime, flow, Synthesis, DFT
Build project schedule, Assemble Design team ,Project & Design team task Management
Work with ASIC PROGRAM MANAGER for keeping program on track
Interact wid cross functional resources on technical issues
Cost management to keep budget control
Job Skills : Design Manager, Physical Design, Virtuoso, Encounter, P & R, PnR, APR, Calibre, Floorplan, IR Drop, Physical Verification, RTL, GDS, Netlist, Timing, STA, Primetime, flow, Synthesis, DFT
Verilog coder for Altera & Xilinx FPGA work
Verilog coder for Altera & Xilinx FPGA work
Verilog coder to develop streaming interface adapters for both the Xilinx Ethernet MAC and the Altera Ethernet MAC.
This means the RX and TX side of the MAC need to be reformatted and adjusted
System Verilog / Specman / Vera Verification Engineer
System Verilog / Specman / Vera Verification Engineer
Embedded/EDA /VLSI/ASIC/Chip Design
BFMs Development, Test case development, Module and SOC level verification and ARM processor Knowledge, expertise in debugging tools is must.
Knowledge on code coverage and functional cover Tool
Job Description
BFMs Development, Test case development, Module and SOC level verification and ARM processor Knowledge, expertise in debugging tools is must.
Good knowledge on code coverage and functional coverge tools
USB, PCIE, AHB/AXI working knowledge.
Design Verification System Verilog
Design Verification - System Verilog
Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).
Proficiency in one or more HVL's System Verilog, C++, Vera, e, System C, Test Builder is a must.
Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AMBA, PHY Layer is a must
Must be expert in building a verification environment with any of the above methodology, writing and debugging test cases.
Should be able to enhance the Verification Coverage, Code coverage & Functional Coverage.
Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc. is a must
SoC Verification Vera System Verilog
SoC Verification - Vera/ System Verilog
Experience : 5+years
Qualification : Any Engineering Graduate
Skill Set : SoC Verification, Vera, System Verilog
ASIC Engineer (VHDL, Verilog HDL,system verilog)
ASIC Engineer (VHDL, Verilog HDL,system verilog)
Application Programming, Maintenance
Fluent in VHDL, Verilog HDL,
At least one project in Design,Should have developed .experience on at least one of the protocol: USB, PCI, PCIe, SONET, Ethernet, AHB/AXI, SATA, OCP, WLAN,Good knowledge of processor based architectures.
Job Description
Fluent in VHDL, Verilog HDL,At least one project in Design,Should have developed design from scratch
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Interaction with overseas client.
Working experience at: USB, PCI, PCIe, SONET, Ethernet, AHB/AXI, SATA, OCP, WLAN,Good
Senior RFIC Design Engineer.
Exp. in yrs.
4+ Yrs
Domain Knowledge
IC Designer Engineering.
Primary Skills
RF Design, RFIC Design Evaluation ,Digital Audio BroadCast(DAB),
BiCMOS
Secondary Skills
DAB & Circuit blocks for Mobile Communication.
Additional comments
Responsible for design of RFIC blocks using Cadence / Hspice, Layout Eng.
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Senior Digital Engineer (Mixed signal Team).
Exp. in yrs.
4+ Yrs
Domain Knowledge
Digital Mixed Signal Engineering
Primary Skills
Mixed Signal as part of LSI Design, Std.
Cell ASIC design(CBIC) with CMOS processes, Mixed Signal / RF.
Secondary Skills
Integrated DRAM.CPU & Logic.
Additional comments
Design mixed signal devices for mobile communications, Design (RTL
level using Verilog )
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ASIC Design Engineer
Exp. in yrs.
3+ Yrs
Domain Knowledge
ASIC Design Engineering.
Primary Skills
VHDL/ Verilog prog. Synthesis & simulation
Secondary Skills
C/C++ Programming
Additional comments
Good understanding of RISC CPU systems & Pipeline
micro-architecture.
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Senior Engineer Manager – R&D
You will Lead and drive the R&D activities of the Company and play a lead Role in developing New business models.
You will have:
Doctorate in electronics / communication with excellent knowledge of VoIP & communication domain. Good background of ASIC design and software design, highly conversant with DSP and voice processing. Should hold to the credit, patents and research projects.
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Senior Program Manager
You will: Interact with multiple agencies working on different tasks, towards achieving a common goal.
You will have:
An engineering degree with an excellent track of scheduling, managing and coordinating multiple projects, with exposure to requirement definition, system architecture, and taking design from initial concept through production for communication systems application. Good exposure to leading project management tools & procedures is a definite plus. Should have exposure to semiconductor ASIC / Embedded software project life cycle. Should possess good people skills.
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Chip Architects
Architects With more than 5 years experience in
Digital IC architecture
Micro architecture
Verification methodology
Proven working chips
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Project Managers - RTL Design
With more than 5 years experience in
RTL design
Verification
Synthesis
Timing closure
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Project Manager ASIC
With more than 5 years experience in
Physical design methodology
Place & route experience
Extraction & verification
Supported by multiple tape outs
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Engineers : Front End Design
You have design experience in
* Verilog coding & test benches
* Synthesis and timing closure
* Use of RISC/ DSP processor hardware
* Architecture of large ASIC’s
Physical Design
You have participated in ASIC tape outs doing
* Place and route
* LVS, DRC
* Extraction – back annotation At 1.0 micron technology or better
Test & Product Engineering
Worked on IC testing having
* Developed test programs for Sentry 21/21,
Credence Vistavision, HP, LTX, etc.,
* Tested chips for continuity, leakage, function, stress,
Idd, VOH / VOL, VIH/VIL, etc.
* Load board, probe card design
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ASIC Design Manager - Pune
Our clients are the first CMMi Level 5 certified software services company in India and leading provider of integrated business, technology and process solutions on a global delivery platform. They have immediate requirement for the following skills for their Pune office.
Location : Pune
Skill Sets :
Bachelors / Masters Degree in Engineering : Electronics / Electrical / with minimum 6 to 10 years experience in Digital Front End Design and ASIC/SoC integration
HDL Languages :
- VHDL, Verilog
- Hands on experience in working with RTL design changes / Integration
- Understanding on Memories and Memory Controllers
DFT basics :
- Concepts of ATPG, JTAG and MBIST
- Hands on experience in Functional and Timing Simulations, debugging gate level simulations
- Familiarity with Cadence / Mentor Simulation Tools, DFT Tools
- Experience in Functional Test Pattern development, Silicon debug interfacing and support Silicon Debug with Testing team.
- Concepts of Synthesis, Static Timing Analysis, preferably Synopsys Tools ( DC, PT).
Configuration Management :
Project Management exposure- Estimations, planning, tracking, customer interactions,
Please send us your latest updated resume with current, expected salary details and required time to join to priya@kbsconsultants.com
Engineer Board Development Group
Required Skills
1. Good understanding of Board design / development issues
2. Expertise in FPGA ‘s using Altera / Xilinx tools 3. Porting / mapping of Hardware IP’s to FPGA devices 4. Schematic entry using OrCad, Parts selection, Timing verification
5. Board design using CAD tools, like OrCad
6. Usage of spectrum analyser, logic analyser
7. Proven expertise in development and testing of high speed board
8. Exposure to Verilog / VHDL
9. Project management skills
Desirable
1. FCC testing
2. Working knowledge of Synplicity tool
3. Good knowledge of testing & debugging, development of diagnostics
4. Good working knowledge of telecommunication / embedded domain
Job Description
To manage to the board development activities, and to interact with the system architecture group & ASIC team, port / map different Hardware IP’s into FPGA devices. Work on schematic entry to design prototype of ASIC on board. Interact with Software team to boot up board & development of diagnostics.
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Principal Digital Design Engineer (Mixed Signal team)
The Role
Working as part of the Mixed Signal team, specific Key Result Areas will
include:
Responsibility for design of sub-systems (consisting of multiple modules):
- specification generation;
- design (RTL level using verilog);
- and implementation (i.e. synthesis and test).
Supervision of 2 to 3 engineers to lead chip design in its entirety.
Project management.
Deliverables.
Core Skills
Achievement Drive Commitment to deliver and a strong sense of ownership.
Specialist Expertise good technical knowledge.
Teamwork & Co-operation Leadership skills will be required in this position
but previous experience is not essential.
Communication Skills Good communications skills. Any experience of
working with the Japanese would be an advantage.
Technical Skills
A degree or equivalent, MSc plus.
5+ years experience.
Must be able to show evidence of design experience (as detailed above) on at least 2 to 3 previous designs.
Digital background (ideally within a mixed signal environment).
Verilog (or VHDL) knowledge.
Any system knowledge in GSM, DECT or mobile communications.
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RFIC Design Engineer
The Role
Key Result Areas that will be part of the role:
Responsibility for design of RFIC blocks using Cadence/ Hspice;
Specification generation and interpretation;
Evaluation of RF chips;
Working with Layout engineers to ensure layout is completed such that track parasitics etc do not effect device performance.
Core Skills
Achievement Drive Commitment to deliver to time scales and a strong sense of ownership Initiative able to work under own initiative.
Specialist Expertise Good grasp of basic RFIC design skills and general
electronic engineering principles.
Teamwork & Co-operation Be able to work successfully with the local and
wider team on project onsite locations
Technical Skills
A degree (or equivalent) in Electronic Engineering or related subject.
2+ years experience.
Must be able to show evidence of design experience in a RFIC environment.
Experience of SPICE type simulation required, using Hspice or similar.
Any RF systems knowledge an advantage.
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Digital Design Engineer (Mixed Signal team)
The Role
Working as part of the Mixed Signal team, specific Key Result Areas will
include:
Responsibility for design of sub-systems (consisting of multiple modules):
specification generation;
design (RTL level using verilog);
and implementation (i.e. synthesis and test).
Supervision of a graduate level engineer.
The Core Skills
Achievement Drive Commitment to deliver and a strong sense of ownership.
Specialist Expertise Good grasp of basic digital design skills.
Initiative Able to work under own initiative.
Teamwork & Co-operation Good team player.
Technical Skills
A degree or equivalent.
2 to 3 years experience.
Must be able to show evidence of design experience (as detailed above) on
at least one previous design.
Digital background (ideally within a mixed signal environment).
Verilog (or VHDL) knowledge
Any system knowledge in GSM, DECT or mobile communications.
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Analogue Design Engineer
The Role
Working as part of the mixed-signal team, specific Key Result Areas will
include:
Design, simulation and characterisation of analogue circuits applied to
mobile communications.
The Core Skills
Achievement Drive – approaches challenges and problems with energy,
enthusiasm and a determination to succeed.
Analytical Thinking – quickly grasps new problems or technical issues,
particularly in circuit analysis.
Initiative – requires only general guidance.
Planning & organising – develops clear and realistic plans to achieve
specific objectives.
Specialist Expertise – must have experience of CMOS analogue design and
knowledge of industry-standard design and simulation tools.
Desirable Technical Skills
A degree in electronic engineering or equivalent.
A minimum of one year experience in the design of analogue CMOS circuits.
Knowledge of signal processing, switched-capacitor circuits and/or
converters (A/D, D/A).
Experience in transistor-level digital design desirable.
Basic knowledge of Verilog HDL for modelling.
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ASIC,VHDL,Verilog, ASIC Design, RFIC Design Engineer, Senior Digital Engineer, Mixed signal, ASIC Design Engineer, R&D, R & D, Research and Development, Digital IC, architecture, Micro architecture, Verification, methodology, chip design, chip architecture, Physical design, physical design methodology, Place & route, place and route, Extraction & verification,extraction, verification, Front End Design,Board Development,FPGA, ASIC,VHDL,Verilog, board design, Digital Design Engineer, Analogue, Analog, design, backend,circuit, circuit blocks, blocks,DAB, Digital audio broadcast,
