Senior RFIC Design Engineer.
Exp. in yrs. 4+ Yrs Domain Knowledge IC Designer Engineering. Primary Skills RF Design, RFIC Design Evaluation ,Digital Audio BroadCast(DAB), BiCMOS Secondary Skills DAB & Circuit blocks for Mobile Communication. Additional comments Responsible for design of RFIC blocks using Cadence / Hspice, Layout Eng.
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Senior Digital Engineer (Mixed signal Team).
Exp. in yrs. 4+ Yrs Domain Knowledge Digital Mixed Signal Engineering Primary Skills Mixed Signal as part of LSI Design, Std. Cell ASIC design(CBIC) with CMOS processes, Mixed Signal / RF. Secondary Skills Integrated DRAM.CPU & Logic. Additional comments Design mixed signal devices for mobile communications, Design (RTL level using Verilog )
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ASIC Design Engineer
Exp. in yrs. 3+ Yrs Domain Knowledge ASIC Design Engineering. Primary Skills VHDL/ Verilog prog. Synthesis & simulation Secondary Skills C/C++ Programming Additional comments Good understanding of RISC CPU systems & Pipeline micro-architecture.
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Senior Engineer Manager – R&D
You will Lead and drive the R&D activities of the Company and play a lead Role in developing New business models.  You will have:  Doctorate in electronics / communication with excellent knowledge of VoIP & communication domain. Good background of ASIC design and software design, highly conversant with DSP and voice processing. Should hold to the credit, patents and research projects.
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Senior Program Manager
You will: Interact with multiple agencies working on different tasks, towards achieving a common goal.  You will have:  An engineering degree with an excellent track of scheduling, managing and coordinating multiple projects, with exposure to requirement definition, system architecture, and taking design from initial concept through production for communication systems application. Good exposure to leading project management tools & procedures is a definite plus. Should have exposure to semiconductor ASIC / Embedded software project life cycle. Should possess good people skills.
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Chip Architects
 Architects With more than 5 years experience in  Digital IC architecture  Micro architecture  Verification methodology  Proven working chips 

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Project Managers - RTL Design
With more than 5 years experience in RTL design 
Verification 
Synthesis 
Timing closure
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Project Manager ASIC
With more than 5 years experience in  Physical design methodology  Place & route experience  Extraction & verification  Supported by multiple tape outs
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Engineers : Front End Design
You have design experience in * Verilog coding & test benches  * Synthesis and timing closure  * Use of RISC/ DSP processor hardware  * Architecture of large ASIC’s Physical Design  You have participated in ASIC tape outs doing  * Place and route  * LVS, DRC  * Extraction – back annotation At 1.0 micron technology or better  Test & Product Engineering Worked on IC testing having  * Developed test programs for Sentry 21/21,  Credence Vistavision, HP, LTX, etc.,  * Tested chips for continuity, leakage, function, stress,  Idd, VOH / VOL, VIH/VIL, etc.  * Load board, probe card design
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ASIC Design Manager - Pune

Our clients are the first CMMi Level 5 certified software services company in India and leading provider of integrated business, technology and process solutions on a global delivery platform. They have immediate requirement for the following skills for their Pune office.

Location : Pune

Skill Sets :
Bachelors / Masters Degree in Engineering : Electronics / Electrical / with minimum 6 to 10 years experience in Digital Front End Design and ASIC/SoC integration

HDL Languages :

• VHDL, Verilog
• Hands on experience in working with RTL design changes / Integration
• Understanding on Memories and Memory Controllers

• Concepts of ATPG, JTAG and MBIST
• Hands on experience in Functional and Timing Simulations, debugging gate level simulations
• Familiarity with Cadence / Mentor Simulation Tools, DFT Tools
• Experience in Functional Test Pattern development, Silicon debug interfacing and support Silicon Debug with Testing team.
• Concepts of Synthesis, Static Timing Analysis, preferably Synopsys Tools ( DC, PT).

Engineer Board Development Group
Required Skills 
1. Good understanding of Board design / development issues  2. Expertise in FPGA ‘s using Altera / Xilinx tools 3. Porting / mapping of Hardware IP’s to FPGA devices 4. Schematic entry using OrCad, Parts selection, Timing verification  5. Board design using CAD tools, like OrCad  6. Usage of spectrum analyser, logic analyser  7. Proven expertise in development and testing of high speed board  8. Exposure to Verilog / VHDL  9. Project management skills
  Desirable 
1. FCC testing  2. Working knowledge of Synplicity tool  3. Good knowledge of testing & debugging, development of diagnostics  4. Good working knowledge of telecommunication / embedded domain
  Job Description
  To manage to the board development activities, and to interact with the system architecture group & ASIC team, port / map different Hardware IP’s into FPGA devices. Work on schematic entry to design prototype of ASIC on board. Interact with Software team to boot up board & development of diagnostics.
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Principal Digital Design Engineer (Mixed Signal team)
The Role
Working as part of the Mixed Signal team, specific Key Result Areas will include: Responsibility for design of sub-systems (consisting of multiple modules): - specification generation; - design (RTL level using verilog); - and implementation (i.e. synthesis and test). Supervision of 2 to 3 engineers to lead chip design in its entirety. Project management. Deliverables.
Core Skills
  Achievement Drive Commitment to deliver and a strong sense of ownership. Specialist Expertise good technical knowledge. Teamwork & Co-operation Leadership skills will be required in this position but previous experience is not essential. Communication Skills Good communications skills. Any experience of working with the Japanese would be an advantage.
Technical Skills 
A degree or equivalent, MSc plus.  5+ years experience.  Must be able to show evidence of design experience (as detailed above) on at least 2 to 3 previous designs.  Digital background (ideally within a mixed signal environment).  Verilog (or VHDL) knowledge.  Any system knowledge in GSM, DECT or mobile communications. 
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RFIC Design Engineer 
The Role 
Key Result Areas that will be part of the role:  Responsibility for design of RFIC blocks using Cadence/ Hspice;  Specification generation and interpretation;  Evaluation of RF chips;  Working with Layout engineers to ensure layout is completed such that track parasitics etc do not effect device performance.
  Core Skills 
Achievement Drive Commitment to deliver to time scales and a strong sense of ownership Initiative able to work under own initiative. Specialist Expertise Good grasp of basic RFIC design skills and general electronic engineering principles. Teamwork & Co-operation Be able to work successfully with the local and wider team on project onsite locations
Technical Skills
  A degree (or equivalent) in Electronic Engineering or related subject. 2+ years experience. Must be able to show evidence of design experience in a RFIC environment. Experience of SPICE type simulation required, using Hspice or similar. Any RF systems knowledge an advantage.
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Digital Design Engineer (Mixed Signal team)
The Role
Working as part of the Mixed Signal team, specific Key Result Areas will include: Responsibility for design of sub-systems (consisting of multiple modules): specification generation; design (RTL level using verilog); and implementation (i.e. synthesis and test). Supervision of a graduate level engineer.
  The Core Skills 
Achievement Drive Commitment to deliver and a strong sense of ownership. Specialist Expertise Good grasp of basic digital design skills. Initiative Able to work under own initiative. Teamwork & Co-operation Good team player.
Technical Skills 
A degree or equivalent.  2 to 3 years experience.  Must be able to show evidence of design experience (as detailed above) on at least one previous design.  Digital background (ideally within a mixed signal environment).  Verilog (or VHDL) knowledge  Any system knowledge in GSM, DECT or mobile communications.
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Analogue Design Engineer 
The Role
Working as part of the mixed-signal team, specific Key Result Areas will include: Design, simulation and characterisation of analogue circuits applied to mobile communications.
The Core Skills
Achievement Drive – approaches challenges and problems with energy, enthusiasm and a determination to succeed. Analytical Thinking – quickly grasps new problems or technical issues, particularly in circuit analysis. Initiative – requires only general guidance. Planning & organising – develops clear and realistic plans to achieve specific objectives. Specialist Expertise – must have experience of CMOS analogue design and knowledge of industry-standard design and simulation tools.
Desirable Technical Skills
A degree in electronic engineering or equivalent. A minimum of one year experience in the design of analogue CMOS circuits. Knowledge of signal processing, switched-capacitor circuits and/or converters (A/D, D/A). Experience in transistor-level digital design desirable. Basic knowledge of Verilog HDL for modelling.
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Hardware design engineers with FPGA design experience Our clients at Chennai, India are looking for experienced hardware design engineers with FPGA design experience.
Hardware design engineers with FPGA design experience

B. Tech./B.E. or higher in Electrical Engineering with VLSI design focus (major/minor). Specialization in the areas of communications, computer architecture, and networking a strong plus. Familiarity with principles of analog design desirable.
Minimum 5 to 8 years (4 to 6 years with M.Tech./M.E.) of professional experience in chip design, preferably targeted for FPGAs RTL coding using Verilog/VHDL, preferably Verilog. Experience in coding, test and debug of module and subsystem-level designs using industry standard EDA simulation tools (such as Modelsim, Questasim, Verilog-XL/NC, Vantage etc). Experience with low power design a plus.
Domain expertise and experience working on connectivity (PCIe, SATA, USB), processor architecture, networking and storage design applications a strong plus.
Experience in ASIC/FPGA (preferably FPGA) implementation such as synthesis (Synplify Pro), layout, place & route and timing analysis using industry standard EDA tools. Experience with large Altera and Xilinx FPGA device implementations (ISE, MaxPlus-II) is highly desired.
Experience with successful board and system-level bring up of the designs in the lab using latest test equipment (oscilloscopes, logic analyzers etc)
Experience with programming (C/C++) and scripting languages/tools (Awk, Perl, Shell) for design and test automation Familiarity with firmware development for embedded processor cores (ARM, ARC etc)
Proper design documentation and version control practices
Strong sense of ownership, urgency and delivery commitment are required
Excellent oral and written communication skills
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